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small INformal Bernieby Bernie Meyerson, IBM Fellow and VP of Innovation

One of the stubborn facts about the laws of physics is that they apply pretty much universally around the globe. When you have spent your career at the forefront of the semiconductor industry by shrinking generation upon generation of chip technology, facing up to the laws of physics, or more aptly having them come home to roost, can be difficult for those who are still on the treadmill of the past.

This is perhaps why a tendency persists among some in the chip industry to continue to reassure users of information technology that Moore’s Law or some vestige thereof survives. This famous axiom, coined by Intel co-founder Gordon Moore, predicts that the number of transistors that can be placed on a chip will double about every two years. Even if this remains true for some short time into the future, it will not continue for several reasons: 1) atoms don’t scale; 2) silicon devices go “quantum mechanical” at dimensions of about 7 nanometers; and 3) light is getting too slow and electrical signaling even slower.

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That’s why a new collaboration between IBM and 3M to develop the industry’s first “glue” that will make it possible to connect a stack of up to 100 separate chips to create one mega-processor represents a significant new alternative to the same old semiconductor industry scaling techniques that are reaching their limit.

After five decades of shrinking silicon technology per Moore’s remarkably accurate prediction, we’ve pretty much shrunk chip features as far as we can. Assuming technology is just arriving at 22 nanometers that leaves coming nodes at roughly 14nm, 9nm, and perhaps around 7nm. That is three ticks of the generational clock which runs about 2+ years per generation. Then we’re done.

In other words, if the semiconductor industry continues to run at the same past rate and pace, in about six years from now silicon device technology will hit a density limit, and the shrinking “game” that’s been played over the past fifty years will be over.

There is no lack of effort around techniques to continue scaling chip dimensions downward, with silicon nanowires, layers of graphene, and carbon nanotubes as just a sampling of the various alternative structures and materials argued to potentially enable further “shrinks.” Nothing yet appears remotely ready to challenge silicon technology at the multi-billion transistor levels of integration required to be a viable replacement. The good news is that once you get beyond arguing that the good old days are still here, you begin to focus on what can and must be done to continue or even improve IT’s yearly march of progress.

For those who make more than chips, it’s well understood that system performance is all anyone ever really cared about. Great system architectures, advanced interconnect fabrics, software, and myriad other factors beyond just transistors and chips contributed to the extraordinary achievements we’ve seen in computing capabilities.  What’s needed are new approaches that move semiconductor technology forward to continue to enable more efficient, powerful and smaller products, from servers to smartphones.

So why is electronic “glue” a solution?

The answer goes back to the fact that light is slow in terms of chip speed. Electrical signals across chips and circuit boards travel at a fraction of the speed of light. Yet at today’s blistering clock frequencies, you can lose hundreds if not thousands of clock cycles in a system waiting for a request for data to go from a logic chip to a remote memory bank and back. Even getting a signal across a single chip within one full machine cycle can be challenge. The problem is that, relatively speaking, you are moving signals long distances across planar surfaces from chip to chip.  What if instead of moving across chips the data were to travel vertically between them?  That’s where glue comes in.

If you take a logic chip, memory chip and other system chips, slim them to one hundredth or less their original thickness, and then glue them one above the other to form a silicon “brick,” then things get interesting.  If at the same time you devise a way to run electrical channels of tremendous density vertically through all these chips, you’ve just wired yourself a new 3D mega-system, where typical inter-chip signaling distances have collapsed by factors of hundreds to thousands. With that collapse, time, energy, and space savings are tremendous, as are performance gains.

The challenge is that heat hates to flow across interfaces, and if you stack 100 chips, there are at least 200 interfaces heat must cross to exit the stack. Enter the 3M-IBM collaboration.

IBM’s long history of radical innovation in the semiconductor space drives us to develop 3D, vertically integrated system “bricks”. In 3M, IBM has found a partner with the depth of materials and chemistry innovation to create the “glue” with the demanding requirements of being highly thermally conductive, electrically insulating and with the right expansion and contraction properties to withstand wide swings in operating temperatures to enable building that silicon brick. It’s a set of simultaneous requirements that’s a bit like asking to meet a really tall short person. But if you want to understand why 3M is likely to overcome these challenges, study how they got to a reusable, nano-encapsulated adhesive that enables Post-It notes.

In theory, a silicon brick of chips containing micro-channel cooling throughout its layers can be scaled to create a system 100 to 1000 times faster than today’s fastest systems given the tremendous density of capabilities integrated within the brick. This is a very different R & D path then where other industry “leaders” are placing their bets at present, but is inevitable in the long term.

What we are seeing here is the emergence of a new era for silicon technology, where small is no longer the Holy Grail, and where the industry changes course to pursue a far more holistic approach to future gains in IT performance.  It is always disruptive, hugely so in fact, when a five-decade long trajectory ends. However, despite this change in the underlying detail of information technology, I would be surprised if we did not see a resurgence of brilliant innovations to make up the gap that the loss of the ability to scale silicon will create. What will change quickly is the mix of those remaining organizations still equipped to pursue this new avenue of progress, and that shake-out is already well under way.

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16 Comments
 
February 7, 2012
3:53 am

I hope we going to see nano computers pretty soon


Posted by: kaipnumestisvorio
 
February 6, 2012
9:06 pm

king will have its own limits. If the current two dimensional size of a chip is the current limit for single layer silicon timing, then when you build enough layers such that you have a cube with the dimensions largest side of today’s chips, you reach the next limit. However, that is potentially hundreds of orders of magnitud


Posted by: ゴヤール
 
January 2, 2012
10:40 pm

Stacking chips would pose at least two interesting challenges: 1) mechanical stability of the interconnects, not to mention the propagation of micro-cracks; and 2) thermal management, i.e. how to keep the chips cool and prevent thermal runaway. Take away the old norms of plastic or ceramic encapsulation as this would create more problems. A potential solution (if i may) that would address both thermal and mechanical stability is a nano-composite material that is flexible and highly thermal conductive.


Posted by: Mannie Austria
 
September 16, 2011
1:55 pm

In looking forward, are we limited by our own perceptions. We seem deal with the cultural aspect of two dimensional logic and with the advent of string theory the concept of multidimensional logic makes sense. If light is to slow can we deal in concepts from a wave function analysis.


Posted by: Terry Francis
 
September 16, 2011
1:19 pm

Peter, It enables a lot more than Moore’s Law would. We think that it enables a revolution in Computer Architecture and in new applications. This is MORE THAN a mere technology play.


Posted by: Phil Emma
 
September 16, 2011
12:14 pm

Perhaps Phil’s comment addresses this, but can we assume the system performance will (potentially) benefit from a 2-high chip stack to the same extent as a “Moore generation” doubling of transistors, since we are doubling the area density? In other words, is it worth the equivalent of a scaling node…or even more…at the system level?


Posted by: Pete Brofman
 
September 16, 2011
10:42 am

3) Systems aren’t uniformly distributed globs of “stuff.” So the limit described doesn’t directly limit the size of the system (the way Rent’s rule would). It’s cores, caches, and other “big stuff” wired together. While many Universities have made contiguous amorphous layers (i.e., without the 100 microm space), this is NOT the kind of high-performance stuff that we make computers out of. And our layer-to-layer wiring pitch is also likely to be relatively coarse (10-100 microns – probably OK for a 100 micron layer-to-layer pitch). We aren’t densely-integrating fine things. We are coarsely integrating large things. It’s computers; not brains.


Posted by: Phil Emma
 
September 16, 2011
10:41 am

2) Suppose that “a” of every unit of area (a<1) in a layer is needed to provide the infrastructure (power, thru-vias, etc) for the structure to be part of a 3D system. Then, even if I let the number of layers in the system be very large, the limit of the "useful" part of the system (that part not there just to support its 3D-ness) approaches 1/a. That is, if 20% of my chip is there to provide 3D infrastructure for the layers above it, then the most stuff we can put into a stack is about 5 chipfulls. Not as bad as it sounds – see #3.


Posted by: Phil Emma
 
September 16, 2011
10:40 am

Maybe the comment was too long. I will do 3 short ones:

1) Bernie – At 100 microns, we get to a centimeter in 100 layers.
Quite a lot actually – see #2.


Posted by: Phil Emma
 
September 16, 2011
10:24 am

Moore’s law is not simply a physics prediction. He was very clear in his original statement that cost is a factor as well. So stacking does appear to fit quite well into his general framework.

Moore’s original statement that transistor counts had doubled every year can be found in his publication “Cramming more components onto integrated circuits”, Electronics Magazine 19 April 1965:

‘The complexity for minimum component costs has increased at a rate of roughly a factor of two per year… Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.’


Posted by: Tom Bloomquist
 
September 16, 2011
10:16 am

My comments aren’t showing up.
Have I been banned from submission already?
This happens on most sites, but it’s never happened this quickly. A new personal record!


Posted by: Phil Emma
 
September 16, 2011
8:55 am

Test


Posted by: Phil Emma
 
September 15, 2011
9:24 pm

Guys, keeping in mind that layers of added chips would be about 100 microns thick, to reach a true cube, assuming the chip is 1cm sq, would require about 10,000 chips be in the stack. That’s far beyond what is anticipated here, so for all intents and purposes, 100 layers will appear to be a slightly thicker base chip. That, and I suspect Phil is pulling our respective legs on the sphere notion:-})


Posted by: Bernie Meyerson
 
September 15, 2011
5:12 pm

Phil,

Yes, a sphere would be more optimal, and would increase the total area available. In the end you still end up with the distance between the farthest endpoints as your limit. We go through this exact problem when wiring supercomputers to maximum number of endpoints within the smallest possible latency.

Bernie ( King-Smith)


Posted by: Bernie King-Smith
 
September 15, 2011
4:18 pm

Bernie – Wouldn’t a sphere be more optimal?


Posted by: Phil Emma
 
September 15, 2011
3:38 pm

Bernie,

I have been waiting for this to come up because of the distances traveled by the electrons in a chip. However, stacking will have its own limits. If the current two dimensional size of a chip is the current limit for single layer silicon timing, then when you build enough layers such that you have a cube with the dimensions largest side of today’s chips, you reach the next limit. However, that is potentially hundreds of orders of magnitude in increased processor capability.

Bernie King-Smith
IBM Corporation
STG Cross-Platform Systems Performance


Posted by: Bernie King-Smith
 
1 Trackback
 
June 21, 2013
1:00 am

[...] Bernie Meyerson, IBM Fellow and VP of Innovation, describes it succinctly when he says: “1) atoms don’t scale; 2) silicon devices go “quantum mechanical” at dimensions of about 7 nanometres; and 3) light is getting too slow and electrical signalling even slower. [...]


Posted by: Why Moore’s law is coming to an end: a brief history | memeburn
 
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