by Bernie Meyerson, IBM Fellow and VP of Innovation
One of the stubborn facts about the laws of physics is that they apply pretty much universally around the globe. When you have spent your career at the forefront of the semiconductor industry by shrinking generation upon generation of chip technology, facing up to the laws of physics, or more aptly having them come home to roost, can be difficult for those who are still on the treadmill of the past.
This is perhaps why a tendency persists among some in the chip industry to continue to reassure users of information technology that Moore’s Law or some vestige thereof survives. This famous axiom, coined by Intel co-founder Gordon Moore, predicts that the number of transistors that can be placed on a chip will double about every two years. Even if this remains true for some short time into the future, it will not continue for several reasons: 1) atoms don’t scale; 2) silicon devices go “quantum mechanical” at dimensions of about 7 nanometers; and 3) light is getting too slow and electrical signaling even slower.
That’s why a new collaboration between IBM and 3M to develop the industry’s first “glue” that will make it possible to connect a stack of up to 100 separate chips to create one mega-processor represents a significant new alternative to the same old semiconductor industry scaling techniques that are reaching their limit.
After five decades of shrinking silicon technology per Moore’s remarkably accurate prediction, we’ve pretty much shrunk chip features as far as we can. Assuming technology is just arriving at 22 nanometers that leaves coming nodes at roughly 14nm, 9nm, and perhaps around 7nm. That is three ticks of the generational clock which runs about 2+ years per generation. Then we’re done.
In other words, if the semiconductor industry continues to run at the same past rate and pace, in about six years from now silicon device technology will hit a density limit, and the shrinking “game” that’s been played over the past fifty years will be over.
There is no lack of effort around techniques to continue scaling chip dimensions downward, with silicon nanowires, layers of graphene, and carbon nanotubes as just a sampling of the various alternative structures and materials argued to potentially enable further “shrinks.” Nothing yet appears remotely ready to challenge silicon technology at the multi-billion transistor levels of integration required to be a viable replacement. The good news is that once you get beyond arguing that the good old days are still here, you begin to focus on what can and must be done to continue or even improve IT’s yearly march of progress.
For those who make more than chips, it’s well understood that system performance is all anyone ever really cared about. Great system architectures, advanced interconnect fabrics, software, and myriad other factors beyond just transistors and chips contributed to the extraordinary achievements we’ve seen in computing capabilities. What’s needed are new approaches that move semiconductor technology forward to continue to enable more efficient, powerful and smaller products, from servers to smartphones.
So why is electronic “glue” a solution?
The answer goes back to the fact that light is slow in terms of chip speed. Electrical signals across chips and circuit boards travel at a fraction of the speed of light. Yet at today’s blistering clock frequencies, you can lose hundreds if not thousands of clock cycles in a system waiting for a request for data to go from a logic chip to a remote memory bank and back. Even getting a signal across a single chip within one full machine cycle can be challenge. The problem is that, relatively speaking, you are moving signals long distances across planar surfaces from chip to chip. What if instead of moving across chips the data were to travel vertically between them? That’s where glue comes in.
If you take a logic chip, memory chip and other system chips, slim them to one hundredth or less their original thickness, and then glue them one above the other to form a silicon “brick,” then things get interesting. If at the same time you devise a way to run electrical channels of tremendous density vertically through all these chips, you’ve just wired yourself a new 3D mega-system, where typical inter-chip signaling distances have collapsed by factors of hundreds to thousands. With that collapse, time, energy, and space savings are tremendous, as are performance gains.
The challenge is that heat hates to flow across interfaces, and if you stack 100 chips, there are at least 200 interfaces heat must cross to exit the stack. Enter the 3M-IBM collaboration.
IBM’s long history of radical innovation in the semiconductor space drives us to develop 3D, vertically integrated system “bricks”. In 3M, IBM has found a partner with the depth of materials and chemistry innovation to create the “glue” with the demanding requirements of being highly thermally conductive, electrically insulating and with the right expansion and contraction properties to withstand wide swings in operating temperatures to enable building that silicon brick. It’s a set of simultaneous requirements that’s a bit like asking to meet a really tall short person. But if you want to understand why 3M is likely to overcome these challenges, study how they got to a reusable, nano-encapsulated adhesive that enables Post-It notes.
In theory, a silicon brick of chips containing micro-channel cooling throughout its layers can be scaled to create a system 100 to 1000 times faster than today’s fastest systems given the tremendous density of capabilities integrated within the brick. This is a very different R & D path then where other industry “leaders” are placing their bets at present, but is inevitable in the long term.
What we are seeing here is the emergence of a new era for silicon technology, where small is no longer the Holy Grail, and where the industry changes course to pursue a far more holistic approach to future gains in IT performance. It is always disruptive, hugely so in fact, when a five-decade long trajectory ends. However, despite this change in the underlying detail of information technology, I would be surprised if we did not see a resurgence of brilliant innovations to make up the gap that the loss of the ability to scale silicon will create. What will change quickly is the mix of those remaining organizations still equipped to pursue this new avenue of progress, and that shake-out is already well under way.